The present invention relates to a decoded (ring) counter (e.g. based on a shift register) which is capable of self-correcting any invalid state that may accidentally be assumed by the counter.
The field of the application of shift registers (SR) is extremely wide and differentiated and includes also counters. In fact, if for example the output of the last edge-triggered, D, flip-flop (FF) of a shift register (SR) is connected to the input of the first flip-flop and if to a reset input of any one of the flip-flops is fed a logic "1", a so-called, "N-module" counter is implemented, where N is the number of flip-flops that form the shift register. A shift-register-based ring counter of this type is schematically shown in FIG. 1.
It is also well known that the above is not a widely used solution for realizing a counter because of several drawbacks, including:
i) Silicon area requirements. An N-module binary counter is normally implemented with a number of flip-flops equal to the integer portion of log.sub.2 (N)+1 (if N is a multiple of 2, a number given by log.sub.2 (N) of flip-flops would be sufficient). By contrast an equivalent counter, made with a shift register, would require an N number of flip-flops. PA1 ii) Power consumption. Because a ring counter requires a larger number of flip-flops, it will more heavily load the timing system (clock signal). PA1 iii) Number of possible states. An N-module, binary counter has 2 k possible states (k is the minimum whole number such that 2 k be .gtoreq.N). Conversely, a ring counter has 2N possible states. In particular, if, because of a disturbance, a unique "1" is lost, or if a second "1" is introduced, the ring counter is no longer capable of "cleaning" itself and to return in a correct state. PA1 A) because of an accidental disturbance, more than a single flip-flop of the shift register may store a logic "1". In this case, the synchronous machine would evolve through a sequence of states that never includes a correct one (that is a single flip-flop storing a logic "1"), and therefore the machine would continue to count, but incorrectly; PA1 B) because of an accidental disturbance, the only logic "1" that shifts through the flip-flop chain forming the shift register may be accidentally erased. In such a case, the synchronous machine would enter a stable state and, unless it is acted upon through a suitable reset signal, the counting process would stop.
Notwithstanding these intrinsic drawbacks and disadvantages, a ring counter may be, and is, advantageously used when extremely fast responses and symmetrical clock/output delays are required. In fact, if we have N signals that must cyclically become "high", one at the time, a solution could be that of using a binary counter followed by a K.fwdarw.N decoder, as depicted in FIG. 2. However, an alternative solution could be that of using an N-module ring counter like the one depicted in FIG. 1.
The latter solution requires a larger number of flip-flops, but in this case, the silicon area that would be required is not much different from the area that would be required by the first solution, as long as N is not too large. In fact, according to the first solution besides K flip-flops, it is necessary to implement a decoder, whose architecture is generally not modularly structured as the circuit of the second solution is. Moreover, the K.fwdarw.N decoder that is required in the case of a binary counter, will introduce delays and will be hard to correctly size so that the outputs will switch-on and off with the same switching times (in other words, symmetry of outputs is difficult to procure).
There is also another problem (which in certain applications assumes a fundamental importance): this is the necessity of ensuring that the outputs do not undergo spurious transitions, i.e. that an output signal should be free of spikes following the switching of other outputs.
Unless an appropriate counting code (e.g. the well known Grey code) is used, it is not easy to ensure that a decoder will be totally exempt from this problem. On the other hand, the use of counting codes which are different from the normal binary representation of numbers complicates the remaining circuitry of the counter.
By contrast, by using a ring counter instead, one could not exclude the possibility that (even though this might be improbable) the ring counter could assume an illegal (invalid) state, as mentioned at point iii) above.
In other words, a ring counter such as the one depicted in FIG. 1 may incur one of the following problems:
In both cases, a ring counter may be thought of as becoming "dirty", and being unable to return to a "clear" condition.
The present invention, in a disclosed embodiment, avoids the first problem by using a set/reset mechanism, rather than the data loopback of the prior art, to provide feedback from the end of the chain to the beginning. The data output of the last stage in the chain drives a set/reset line which is connected to a set input of the first stage, and to reset inputs of all other stages. Thus when a "1" propagates through to the last stage, any other propagating "1" bits are extinguished. The second problem is solved by a wired-OR arrangement which is driven by an additional output of each stage, to detect a stable all-zeros state.
Thus the present invention, in a disclosed embodiment, provides a decoded counter employing a shift register and a zero-detect circuit in order to return to a correct state within a limited number of clock cycles whenever an invalid state is accidentally assumed by the counter. One of the flip-flops is provided with synchronous set while all the other flip-flops of the shift register are provided with synchronous reset. The output of the last flip-flop of the register drives a single set-reset line common to all the flip-flops and the pull-up line of the zero-detect circuit is connected to the input of the first flip-flop of the register. Optionally, one of the flip-flops may be provided with asynchronous set and the others with an asynchronous reset, for initializing the counter in a certain state through a single clear-load line.
According to a disclosed class of innovative embodiments, there is provided: A decoded counter circuit, comprising: a plurality of flip-flops chained together, with each intermediate one of the flip-flops having a data input which is connected to a data output of an immediately preceding stage, and a set/reset line which is operatively connected to all of the flip-flops, in a configuration which drives the respective data outputs of the first flip-flop in the chain into a first state when the set/reset line is in an active state, and which drives the respective data outputs of all other the flip-flops in the chain into a second state when the set/reset line is in an active state; the last the flip-flop in the chain having the data output thereof connected to drive the set/reset line.
According to another disclosed class of innovative embodiments, there is provided: A decoded counter circuit, comprising: a plurality of data storage stages chained together, with each intermediate one of the stages having a clock input, a data input, and a data output which corresponds to the data input when the clock input receives a predetermined clock waveform portion, the data input thereof being connected to a data output of an immediately preceding stage, and a set/reset line which is operatively connected to all of the stages, in a configuration which drives the respective data outputs of the first stage in the chain into a first state when the set/reset line is in an active state, and which drives the respective data outputs of all other the stages in the chain into a second state when the set/reset line is in an active state; the last the stage in the chain having the data output thereof connected to drive the set/reset line.
According to another disclosed class of innovative embodiments, there is provided: A decoded counter circuit, comprising: a plurality of logic stages chained together, with each intermediate one of the stages having a data output which corresponds to a clocked version of a data input thereof, the data input being connected to the data output of an immediately preceding stage, and an additional output which is inactive whenever neither the data input nor the data output have the first state; and a set/reset line which is operatively connected to all of the stages, in a configuration which drives the respective data outputs of the first stage in the chain into a first state when the set/reset line is in an active state, and which drives the respective data outputs of all other the stages in the chain into a second state when the set/reset line is in an active state; the last stage in the chain having the data output thereof connected to drive the set/reset line; a wired-logic combining stage which is connected to receive the additional outputs of all of the stages, and which drives the set/reset line active if all of the additional outputs remain inactive.
According to another disclosed class of innovative embodiments, there is provided: A decoded counter circuit, comprising: a plurality of multiplexed-input-flip-flops chained together, with each intermediate one of the flip-flops having a first data input which is connected to a data output of an immediately preceding stage, and a second data input which is connected to a data output of an immediately succeeding stage, and a select input which selects between the first and second data inputs; an up/down line which is operatively connected to the select inputs of all of the flip-flops; a set/reset line which is operatively connected to all of the flip-flops, in a configuration which drives the respective data outputs of the first flip-flop in the chain into a first state when the set/reset line is in an active state, and which drives the respective data outputs of all other the flip-flops in the chain into a second state when the set/reset line is in an active state; the set/reset line being operatively connected to be driven by the data output of a first one of the flip-flops in the chain when the up/down line is in a first state, and by the data output of another one of the flip-flops in the chain when the up/down line is in a second state.
According to another disclosed class of innovative embodiments, there is provided: A decoded counter with self-correction capability, comprising: a shift register composed of an n flip-flops, one of which is provided with a synchronous set while all the others are provided with respective synchronous re-set inputs and wherein the output of the last flip-flop of the shift register drives a single set-reset line common to all the flip-flops; and a zero-detect circuit having a pull-up line functionally connected to an input of the first flip-flop of the register.